Generally, a memory system comprises a memory controller and a dynamic random access memory (DRAM). The memory controller is connected with the DRAM. The memory controller can write data into the DRAM or read data from the DRAM. For example, a double data rate DRAM (also abbreviated as DDR DRAM) is one of the common DRAMs.
FIG. 1 schematically illustrates the architecture of a conventional memory system. The memory system 100 comprises a memory controller 120 and a DDR DRAM 110. Moreover, plural pins of the memory controller 120 are connected with corresponding pins of the DDR DRAM 110 in order to transmit plural control signals. The DDR DRAM 110 is a low power third generation DDR DRAM (also abbreviated as LPDDR3 DRAM) or a low power fourth generation DDR DRAM (also abbreviated as LPDDR4 DRAM).
As shown in FIG. 1, the control signals include a clock enable signal CKE, a clock signal CLK, a command signal CMD and a chip select signal CS. The command signal CMD at least contains seven command address signals CA0˜CA6. That is, 7 pins are employed to transmit the command signal CMD.
The specifications of the LPDDR3 DRAM will be described as follows. For controlling the LPDDR3 DRAM to enter a self-refresh state, the memory controller 120 has to generate an entering self-refresh command SRE. For controlling the LPDDR3 DRAM to exit the self-refresh state, the memory controller 120 has to generate an exiting self-refresh command SRX. Moreover, when the LPDDR3 DRAM enters/exits the self-refresh state, the LPDDR3 DRAM has to enter/exit a power down state. The clock enable signal CKE is employed to control the LPDDR3 DRAM to enter/exit the power down state.
FIG. 2A schematically illustrates the contents of an entering self-refresh command SRE and an exiting self-refresh command SRX for controlling the LPDDR3 DRAM. In response to the rising edge of the clock signal CLK, the entering self-refresh command SRE indicates that the chip select signal CS is in the high level state (H), the command address signals CA0˜CA5 of the command signal CMD are all in the low level state (L) and the command address signal CA6 is in the high level state (H). In response to the rising edge of the clock signal CLK, the exiting self-refresh command SRX indicates that the chip select signal CS is in the high level state (H) and don't care the level states (X) at the command address signals CA0˜CA6.
Moreover, another type of the command signal CMD includes a valid command Valid or a no operation command NOP. For example, the valid command Valid is a read command or a write command.
FIG. 2B is a schematic timing waveform diagram illustrating associated signals for controlling the LPDDR3 DRAM to enter/exit the self-refresh state.
In response to the rising edge of the clock signal CLK at the time point t1, the memory controller 120 generates the entering self-refresh command SRE when the clock enable signal CKE is in the low level state and the chip select signal CS is in the high level state. That is, at the time point t1, the LPDDR3 DRAM enters the self-refresh state and the power down state simultaneously.
In response to the rising edge of the clock signal CLK at the time point ta, the memory controller 120 generates the exiting self-refresh command SRX when the clock enable signal CKE is in the high level state and the chip select signal CS is in the high level state. That is, at the time point ta, the LPDDR3 DRAM exits the self-refresh state and the power down state simultaneously.
As mentioned above, in the time interval between t1 and ta, the self-refresh state of the LPDDR3 DRAM is also the power down state of the LPDDR3 DRAM. Moreover, in the power down state, the memory controller 120 can selectively change the frequency of the clock signal CLK or inactivate the clock signal CLK.
In comparison with the LPDDR3 DRAM, the LPDDR4 DRAM enters/exits the power down state during the self-refresh state. That is, the LPDDR4 DRAM does not have to enter/exit the self-refresh state and the power down state simultaneously. For example, after entering the self-refresh state, the LPDDR4 DRAM enters the power down state. Moreover, after exiting the power down state, the LPDDR4 DRAM exits the self-refresh state.
The specifications of the LPDDR4 DRAM will be described as follows. For controlling the LPDDR4 DRAM to enter a self-refresh state, the memory controller 120 has to generate two consecutive entering self-refresh commands SRE1 and SRE2. For controlling the LPDDR4 DRAM to exit the self-refresh state, the memory controller 120 has to generate two consecutive exiting self-refresh commands SRX1 and SRX2. Moreover, the clock enable signal CKE is employed to control the LPDDR3 DRAM to enter/exit the power down state.
FIG. 3A schematically illustrates the contents of an entering self-refresh command SRE and an exiting self-refresh command SRX for controlling the LPDDR4 DRAM. In response to a first rising edge of the clock signal CLK, the first entering self-refresh command SRE1 indicates that the chip select signal CS is in the high level state (H), the command address signals CA0˜CA2 of the command signal CMD are in the low level state (L), the command address signals CA3˜CA4 are in the high level state (H) and the command address signal CA5 is in a valid level state (V). In response to a second rising edge of the clock signal CLK, the second entering self-refresh command SRE2 indicates that the chip select signal CS is in the low level state (L) and the command address signals CA0˜CA5 of the command signal CMD are all in the valid level state (V). The valid level state (V) is the low level state (L) or the high level state (H).
In response to a first rising edge of the clock signal CLK, the first exiting self-refresh command SRX1 indicates that the chip select signal CS is in the high level state (H), the command address signals CA0, CA1 and CA3 of the command signal CMD are in the low level state (L), the command address signals CA2 and CA4 are in the high level state (H), and the command address signal CA5 is in a valid level state (V). In response to a second rising edge of the clock signal CLK, the second exiting self-refresh command SRX2 indicates that the chip select signal CS is in the low level state (L) and the command address signals CA0˜CA5 of the command signal CMD are all in a valid level state (V).
Similarly, another type of the command signal CMD includes a valid command Valid or a no operation command NOP.
FIG. 3B is a schematic timing waveform diagram illustrating associated signals for controlling the LPDDR4 DRAM to enter/exit the self-refresh state.
In response to the rising edge of the clock signal CLK at the time point t0, the memory controller 120 generates the first entering self-refresh command SRE1 when the clock enable signal CKE is in the high level state and the chip select signal CS is in the high level state. Then, in response to the rising edge of the clock signal CLK at the time point t1, the memory controller 120 generates the second entering self-refresh command SRE2 when the clock enable signal CKE is in the high level state and the chip select signal CS is in the low level state. That is, at the time point t1, the LPDDR4 DRAM enters the self-refresh state.
In response to the rising edge of the clock signal CLK at the time point t3, the clock enable signal CKE from the memory controller 120 is in the low level state. That is, at the time point t3, the LPDDR4 DRAM enters the power down state. Similarly, in the power down state, the memory controller 120 can selectively change the frequency of the clock signal CLK or inactivate the clock signal CLK.
In response to the rising edge of the clock signal CLK at the time point ta, the clock enable signal CKE from the memory controller 120 is in the high level state. That is, at the time point ta, the LPDDR4 DRAM exits the power down state.
In response to the rising edge of the clock signal CLK at the time point tb, the memory controller 120 generates the first exiting self-refresh command SRX1 when the clock enable signal CKE is in the high level state and the chip select signal CS is in the high level state. Then, in response to the rising edge of the clock signal CLK at the time point tc, the memory controller 120 generates the second exiting self-refresh command SRX2 when the clock enable signal CKE is in the high level state and the chip select signal CS is in the low level state. That is, at the time point tc, the LPDDR4 DRAM exits the self-refresh state.
As mentioned above, the LPDDR4 DRAM is in the self-refresh state in the time interval between t1 and tc, and the LPDDR4 DRAM is in the power down state in the time interval between t3 and ta.
In accordance with another conventional method, the clock enable signal CKE is in the low level state at the time point t1 and in the high level state at the time point tc. Consequently, the LPDDR4 DRAM is in the self-refresh state and the power down state simultaneously.
However, a new DDR DRAM maybe introduced into the market. The new DDR DRAM has a new DRAM interface without the clock enable signal CKE pin to transmit the clock enable signal CKE. In other words, the new DDR DRAM cannot enter/exit the power down state according to the clock enable signal CKE.